The rp7405/rp7410 N4000 servers are up to 8-way multiprocessing servers and the smallest HP systems which can be partitioned into logical servers (two nPartitions). Based upon the same 10U rack-mountable chassis as their rp7400/N4000 brethren, the newer rp7405 and rp7410 are built around a completely overhauled system and I/O architecture. The Core Electronic Complex is a modified version of the Superdome’s cell-based system architecture, limited to two cells, which each contain up to four processors, sixteen memory slots and the central chipset — the cell controller (CC). These newer N4000s feature a very large amount of system and I/O bandwidth: 16GB/s CPU, 8GB/s memory, 8GB/s cell-to-cell and 8.5GB/s I/O bandwidth (all maximum aggregate ＆#118alues).
The rp7405 was apparently an entry-level version of the rp7410 — based on the same hardware and with the same capabilities but shipped in smaller configurations. Upgrades to a full rp7410 were later possible, probably including a modified firmware for unlocking the full functionality.
The rp7405 and rp7410 support from two to eight processors.
They are based on different system boards with different model numbers — the same basic architecture but with differences relating to the type and number of processors.
- A6752A (rp7410) supports 650MHz, 750MHz and 875MHz processors
Processor types are indicated with the following suffixes:
- -7X: PA-8700 750MHz with 768/1536KB on-chip I/D L1 cache each
- Itanium 2/IA64 processors are probably also possible on some models
- It is unclear which models support the -8X, -9X, PA-8900 and IA64 processors
There are two CPU/memory cell boards, with each four processor sockets.
The Cell system architecture has three main components:
1. Cell controller (CC): the central chipset and crossbar. One sits at the centre of each cell board for a maximum of two in a complete system. The CCs provide links for:
o Four Processors (8.0GB/s)
o Two Memory banks (4.0GB/s peak)
o I/O via SBA (cell to I/O communication is 2.0GB/s peak)
o PDH (processor dependent hardware) and firmware/flash etc.
o Second cell via XBC (cell-to-cell communication is 8.0GB/s peak)
2. Master I/O controller (SBA): the central I/O part of the main chipset. rp7405/rp7410 have two SBAs, located on the I/O backplane. Each is linked to one cell — with one cell board only one SBA and its I/O options can be used.
o Each SBA provides sixteen 12-bit links (ropes) — the combined 32 (2×16) links/ropes from both SBAs connect to 18 slave I/O controllers (LBAs) which in turn connect the PCI I/O slots and Core I/O subsystems
o 28 ropes link to 14 Twin-Turbo slots (via 14 LBAs)
o Two ropes link to two Turbo (that is, normal) PCI slots (via two LBAs), from which one is reserved for the PCI Core I/O LAN/SCSI card
o Two links/ropes (one from each SBA) are connected via two LBAs to the Core I/O MP/SCSI card(s)
3. Core I/O card set: provides the standard I/O functions for the system. One of these sets is the required minimum in any N4000, up to two Core I/O card sets are possible. Each Core I/O card set contains two distinct cards: MP/SCSI card, installed in a separate slot, and LAN/SCSI, installed in PCI slot (specially designated, I/O chassis 1, slot 8).
o Two dual-channel Symbios Logic 53C1010 Ultra160 SCSI controllers (on MP/SCSI and LAN/SCSI)
o Dual-channel Symbios Logic 53C896 Ultra2-Wide SCSI-3 controller (MP/SCSI)
o Gigabit Ethernet networking (LAN/SCSI)
o Diva Serial [GSP] Multiport UART for console (MP/SCSI), serial and management controllers (MP/SCSI)
o Fast-Ethernet (DEC 21142/43) Management LAN (MP/SCSI)
o The optional second Core I/O card set can be used either for redundancy or partitioning purpuses (I/O for the second partition)
Other parts of the chipset:
- Prelude SMC memory controllers (on each cell board)
- 18 Elroy PCI bridges (LBAs) convert the links/ropes from the SBA into PCI bus (only 9 of these 18 LBAs are used when only one cell board is installed)
» View a system-level illustration (ASCII) of the rp7405/rp7410 system/bus architecture.
- Runway+/Runway DDR CPU bus (CPU to cell controller), 125MHz DDR, 64-bit wide, 2.0GB/s per CPU — aggregate 8.0GB/s for each cell (four CPUs/cell) and 16.0GB/s for maximum system
- Memory bus (memory to cell controller) 4.0GB/s for each cell — aggregate 8.0GB/s for maximum system
- XBC cell-to-cell link (cell controller to cell controller) 8.0GB/s aggregate
- SBA cell-to-I/O link (cell controller to I/O backplane) 2.0GB/s on each cell — aggregate 4.0GB/s for maximum system
- 32 I/O links/ropes, 12-bit wide, 265MB/s (16 links/ropes on each cell) — 8.5GB/s I/O aggregate peak bandwidth
- 14 PCI-64/66 I/O buses for expansion slots
- Two PCI-64/33 I/O buses for expansion slots (for Core I/O SCSI/LAN)
- Two PCI-64/33 I/O buses for Core I/O (MP/SCSI)
- Two SCSI-3 Ultra160 LVD main storage I/O buses (one on each cell)
- Ultra SCSI SE for removable media (DVD/Tape)
- ECC DIMMs, low-voltage TTL interface, 125MHz frequency (traditional/PC-133 SDRAMs do not work)
- 256MB, 512MB and 1GB modules supported (2GB probably later too)
- 16 slots on each cell board (32 slots maximum in a full system configuration), installed in quads
- 32GB maximum (in a full system configuration with two cells)
- 64GB was given as maximum with future memory modules — probably working today
There are in all 16 PCI 64-bit/66MHz slots in the I/O cage, which can be fully accessed when using a system with two cells — with one cell board only seven slots are available. One PCI slot is dedicated to the Core I/O card set (see above) so only 15 of the 16 PCI slots are available for expansion options.
- 14 Twin-Turbo PCI 64-bit/66MHz slots, each on an independent PCI bus, each connected via two I/O links/ropes (aggregate 530MB/s), hot-plug capable
- Two Turbo PCI 64-bit/66MHz slots, each on an independent PCI bus, each connected via one I/O link/rope (265MB/s), hot-plug capable (one of these two Turbo slots is reserved for Core I/O LAN/SCSI)
- Twelve slots keyed for 3.3V (support either 3.3V or universal PCI cards)
- Four slots keyed for 5.0V (support either 5.0V or universal PCI cards)
- Four trays for low-profile 3.5″ Ultra2-Wide LVD SCSI hard drives with 80-pin SCA connector, hot-plug (two Core I/O card sets are needed to access all four drives)
- One tray for a half-heigth 5.25″ 50-pin Ultra-Narrow SE SCSI drive, external accessible
The two pairs of SCSI drives are each connected to a separate channel on one of the SCSI controllers of the Core I/O sets — for both pair of drives to work two Core I/O card sets are needed.
- 68-pin VHDCI Ultra160 LVD external SCSI (external channel from LAN/SCSI board)
- Three DB9 male RS232C serial (local console, remote console, UPS) via a DB25 M cable (MP/SCSI board)
- 10/100Mbit Ethernet TP/RJ45 Management LAN (MP/SCSI board)
- Gigabit Ethernet TP/RJ45 (LAN/SCSI board)
There is an firmware update available which contains the latest version version 6.5.
- PF_CKEYMAT0605.txt has details about the contents and installation of the patch.
- PF_CKEYMAT0605.tar.gz contains the patch.
- User Guide hp rp7405/7410 Servers (PDF) Hewlett-Packard Company (2002, third edition)
- hp server rp7410 whitepaper, Hewlett-Packard Company (March 2002, product number 5980-9997EN) [did not find an appropriate URL for this PDF document —Ed.]
- HP-UX: 11i (v1, v2 and v3) (11.00 unsure and officially unsupported)
- Linux: should work
Compare these with other results on the Benchmarks page.
- Rack-mounted: 10U height
- Up to two hot-swappable/redundant power supplies (one is standard)